1. Field of the Invention
The present invention generally relates to a method and an apparatus of priority arbitration, and more particularly to a method and an apparatus of arranging priority queue for an arbiter within a memory access interface.
2. Description of the Related Art
As the requirement of consumer media electronic products increases, in order to enhance the product competition, the concept of SoC (System On Chip) has become a trend. Due to the device integrated, the chip with SoC concept has less power consumption, greater heat dissipation, and better signal transmission quality. Moreover, the concept of SoC puts more and more devices into one single chip, so each device in this chip has to be integrated or reduced its size in order to meet the requirement of SoC. With the integration of devices, the use of devices and substrates can be reduced. Due to the size reduction of devices, the volume of chip is reduced, and also the package is reduced, so the cost of the chip designed with the concept of SoC can be reduced. One of the most widely used consumer media electronic products is multi-media player.
In order to process different types of video and audio signals, a well-known multi-media player comprises many microprocessors with different functions, for example, a video decoder unit is necessary to process video signals; a digital signal processor (DSP) is necessary to process audio signals. Additionally, amounts of memory modules are needed for a well-known multi-media player to handle large data transportation and storage of firmware.
A memory interface exists between microprocessor and its corresponding memory modules for establishing contact in the access. To make requests accessing efficient, the memory interface comprises an arbiter, determining which one of the access requests asked by the microprocessor has the priority and deciding which one of the access requests can use the bus bandwidth. Before arbitrating the priority of bus bandwidth, a standard of bus bandwidth sequence which is called priority queue must be setup. It decides which one of the access requests has the priority to use bus bandwidth based on priority queue when a plurality of access requests are asking at the same time.
A well-known arrangement of queue is shown in FIG. 1 with a concept of first in first out (FIFO). The first asked access request has the highest priority, which is arranged in forefront (front in queue) position and must be executed firstly. After finishing executing the forefront access request, the other access requests are pushed forward and a new access request is added into the last position (rear in queue) of the queue.
Because of the trend of the concept of SoC (System On Chip) and reduction of memory space in systems, an invention of sharing memory address and data buses is provided earlier, where some parts of system with same functions are integrated or shared. All microprocessors have to access shared memory and data buses via a shard memory interface in the system. Therefore a better method of arranging priority queue and an efficient arbitrative apparatus is necessary to decide the request priority of a system with amounts of access requests. Consequently, system performance is increased.